\section{Introduction and Motivation}\label{sec:intro}
Memristor was first theoretically predicted by Chua several decades
ago~\cite{memristor:chua}, as the fourth basic passive circuit element in
addition to resistor, capacitor, and inductor. The real memristor
implementation, however, was not demonstrated until recently. HP Labs
found a way to implement the memristor using a two-terminal, two-layer
semiconductor with layers of titanium oxide sandwiched between two metal
electrodes in a crossbar architecture~\cite{memristor:missing}. By
applying an external voltage across the device, the memristor can switch
between two stable states: ON state with low resistance and OFF state with
high resistance. A positive voltage above a specific threshold will switch
the device into the OFF state (RESET operation) and a negative voltage of
the same magnitude toggles it to its ON state (SET operation). The
memristor-based memory can be thought of as a particular kind of the
emerging Resistive Random Access Memory (ReRAM)
technology~\cite{memristor:pengli}, which has shown great potentials as
one of the most promising memory technologies, with the unique properties
such as high density, low-power, good-scalability, and non-volatility. HP
labs and Hynix have already announced that they are going to commercialize
the memristor-based memory and predicted that ReRAM could eventually
replace traditional memory technologies~\cite{memristor:HpHynix}.

Memristor-based memory has been proposed by Ho~\cite{memristor:pengli}.
There are two possible memory organizations for memristor-based memory:
\begin{enumerate}

\item \noindent\textbf{Memory Array Structure.} In the memristor-based
    memory array, the conventional memory cell is substituted by the
    memristor where the access device remains to be the MOSFET. This is illustrated
    in Figure~\ref{fig:arch0}(a). In this structure, since each memristor
    cell has to be accompanied with a MOSFET access device whose size is much
    larger than the memristor, the memory cell size is mainly dominated by MOSFET
    access device rather than the actual memristor, and therefore the
    area efficiency is affected.

\item \noindent\textbf{Cross-Point Structure.} The cross-point array
    is a more area-efficient structure for the memristor-based
    ReRAM~\cite{memristor:Cong}. In the cross-point array, the only
    item at each crossing point is the memristor cell. Therefore, the
    area of the array is significantly reduced since the large MOSFET
    access part is removed. For the cross-point structure, a two-step
    writing methodology, ERASE-before-RESET, is used to prevent the
    unintended writing. In read operation two ways are exhibited for
    preventing a read failure: the first is to supply the same voltage
    to the unselected row and selected column. In this way, only the
    data on the select row is read from the selected column. The
    disadvantage of this method is the voltage drop on the crossing
    points of the unselected row and the selected column may not be
    ideal zero because of variations, and this imposes a limitation on
    the array size. The second way is a two-step write operation. The
    disturbance current of the partial selected cell on the selected
    column will be read out beforehand as a background current. Later
    the total current, comprised of both partial selected cell and
    full selected cell, will be read out. The state of the selected
    cell can then be determined by computing the difference between
    the total current and background current.
\end{enumerate}
\begin{figure}
\centering
  % Requires \usepackage{graphicx}
  \includegraphics[width=0.5\textwidth]{./figures/memristor_conv_array.pdf}\\
  \vspace{-5pt}
  \caption{Structures of memory array of memristor. (a) The schematic view of MOS-accessed array. (b) The schematic view of cross-point memory array. (WL=wordline, BL=bitline, SL=sourceline) }\label{fig:arch0}
  \vspace{-15pt}
\end{figure}


The memristive switching behaviors have been observed in many MIM
nanodevice with different materials. However, the switching mechanism of
the MIM nanodevice is still unknown. One of the most possible reasons is
that different mechanisms may affect the nanodevice simultaneously and it
is hard to distinguish the effect of certain mechanism. In addition, even
a certain mechanism may affect the device with different materials at very
different degrees, which further exacerbates the possibility to extract a
universal model for all of the MIM nanodevices. However, the switching
mechanism of $TiO_2$ based MIM nanodevice, namely memristor, has been well
studied~\cite{memristor:mechanism}. Therefore, in this paper, we mainly
focus on the memristor-based ReRAM. However, the concept and methodology
can be easily applied to other MIM device based ReRAM designs. Similar to
the problem with other nanoscale devices, the impact of process
variability is also critical to the memristor-based memory. The impact of
process variations on the electrical properties of different memristors
has been addressed and analyzed in~\cite{memristor:dimin}
and~\cite{memristor:ASPDAC}. It has been reported that, under the impact
of all of these variations, the switching time of memristor cells with
identical internal structure follows a log-normal distribution. The
probability density function (PDF) and the cumulative distribution
function (CDF) can be expressed as:

\vspace{-10pt}
%\begin{eqnarray}
\begin{align}
\label{equ:CDF}
f(t; \tau, \sigma) & = \frac{1}{\sqrt{2\pi}t\sigma}\textmd{exp}[-\frac{(\textmd{ln}(t/\tau))^2}{2\sigma^2}]\\
F(t; \tau, \sigma) & = \frac{1}{2}{\textmd{erfc}}[-\frac{(\textmd{ln}(t/\tau))}{\sqrt{2}\sigma}],
\end{align}
%\end{eqnarray}
where $t$ is the switching time of the memristor cell, $\tau$ is the
median switching time under certain external bias voltage, and $\sigma$ is
the standard deviation of $\tau$. Also, the median switching time has an
exponential dependency to the external voltage, and there is no
significant relationship between the standard deviation $\tau$ and the
voltage~\cite{memristor:logarithm}. Figure~\ref{fig:cdf} shows the PDF and
CDF of switching time under different external bias voltage. It can be
easily observed that a higher input voltage will increase the probability
of shorter switching time significantly. Therefore, increasing the
programming voltage is a good method to improve the reliability of the
memristor-based memory. Besides, for a given voltage constraint, the
switching probability of a memristor cell increases with the switching
time. Therefore, we can also increase the write latency to satisfy the
relatively high reliability requirement of a memory cell.

%large write
%latency will also benefit the reliability of the memristor cell.

\begin{figure}
\centering
  % Requires \usepackage{graphi cx}
%  \includegraphics[width=0.5\textwidth]{./figures/cdf_sim.pdf}
    \includegraphics[width=0.35\textwidth]{./figures/cdf_shu.pdf}
  \vspace{-10pt}
  \caption{CDF and PDF of the switching time under different voltage input}\label{fig:cdf}
  \vspace{-15pt}
\end{figure}

The uncertainty of switching time for ReRAM cell will cause write failures
during the write operation, and results in data error of a ReRAM based
memory array. Since the error rate is closely related to the materials of
the ReRAM cell, the program voltage, as well as the program duration, it
may be much higher than those of the traditional memory technologies under
certain design constraints. Traditional Error Correction Code (ECC)
circuit design for conventional DRAM memory may not be able to ensure the
correct functionality of ReRAM-based memory due to much higher error
rates. Consequently, a stronger error correcting code is needed, which
results in a large energy/area overhead, offsetting the density/power
benefits offered by the ReRAM memory technology.\textbf{ In this work, we
build a mathematical model of the error pattern for the ReRAM cell, and
analyze the error rate of the whole ReRAM-based memory array. Based on the
analysis, various ECC design schemes are investigated to relax the
reliability requirement of the memristor cell and therefore improve the
performance and energy efficiency of the ReRAM-based memory system}.

%The rest of this paper is organized as follows. In
%Section~\ref{sec:preliminaries}, the memristor-based memory and the basic
%concept of ECC are introduced. Section~\ref{sec:mathematical} discusses the mathematical model used in this paper and evaluates various ECC
%designs for memristor-based ReRAM architecture. Section~\ref{sec:experiment} shows results of the experiment conducted in this study. Finally, the conclusion is presented in Section~\ref{sec:conclusion}.
